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Processor | |
Processor model | X5260 |
Processor front side bus | 1333 MHz |
Processor lithography | 45 nm |
Processor family | Intel® Xeon® 5000 Sequence |
Box | ![]() |
Processor socket | LGA 771 |
Stepping | C0 |
Processor cores | 2 |
Processor code | SLANJ |
L2 cache speed | 3.33 |
CPU multiplier (bus/core ratio) | 10 |
Processor operating modes | 64-bit |
Component for | Server/workstation |
Processor cache | 6 MB |
Processor frequency | 3.33 GHz |
Processor cache type | L2 |
Processor system type | DP |
Energy management | |
VID Voltage Range | 0.95 - 1.2125 V |
Thermal Design Power (TDP) | 80 W |
Operational conditions | |
Maximum operating temperature | 66 °C |
EAN | |
Warranty | 1 year |
Source: Icecat.biz |
The Dual-Core Intel® Xeon® Processor 5200 Series is a server/workstation processor utilizing two 45-nm Hi-k next generation Intel® Core™ microarchitecture cores. The processor is manufactured on Intel’s 45 nanometer process technology combining high performance with the power efficiencies of a low-power microarchitecture. The Dual-Core Intel® Xeon® Processor 5200 Series maintains the tradition of compatibility
with IA-32 software. Some key features include on-die, primary 32-kB instruction cache and 32-kB write-back data cache in each core and 6 MB Level 2 cache with Intel® Advanced Smart Cache architecture. The processors’ Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting in reduced
effective bus latency and improved performance. The 1333 MHz Front Side Bus (FSB) is a quad-pumped bus running off a 333 MHz system clock making 10.66 GBytes per second data transfer rates possible. The 1600 MHz Front Side Bus (FSB) is a quadpumped bus running off a 400 MHz system clock making 12.80 GBytes per second data transfer rates possible.
with IA-32 software. Some key features include on-die, primary 32-kB instruction cache and 32-kB write-back data cache in each core and 6 MB Level 2 cache with Intel® Advanced Smart Cache architecture. The processors’ Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting in reduced
effective bus latency and improved performance. The 1333 MHz Front Side Bus (FSB) is a quad-pumped bus running off a 333 MHz system clock making 10.66 GBytes per second data transfer rates possible. The 1600 MHz Front Side Bus (FSB) is a quadpumped bus running off a 400 MHz system clock making 12.80 GBytes per second data transfer rates possible.
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